vivado clock IP

create new project, select board

project manager -> IP catalog -> search clock -> double click clocking wizard

set input clock

set output clock

summary

press generate

open clk_wiz_0.v

//create testbench file, copy input output pins

//testbench.v

`timescale 1ns / 1ps

module testbench;

wire clk_out1, clk_out2, clk_out3, locked;   

reg reset, clk_in1;

clk_wiz_0 UUT(clk_out1, clk_out2, clk_out3, reset, locked, clk_in1);     

initial begin

clk_in1 = 0;

#5 reset = 1;

#5 reset = 0;

end

always #5 clk_in1=~clk_in1; //100MZ

endmodule

zoom in after clocks are stable (locked=1)

clk_in 10ns 100MZ

clk_out_1 20ns 50MZ

clk_out_2 20ns 50MZ 75% duty cycle

clk_out_3 5ns 200MZ

reference:

https://www.youtube.com/watch?v=KnRoSdcgBAA