vivado rgb light

//add source -> verilog file

//rgb.v

`timescale 1ns / 1ps

module rgb(

    input wire [3:0] switch,

    output wire red,

    output wire green,

    output wire blue

    );

    

assign red = ~switch[3] & ~switch[2];

assign blue = (~switch[3] & switch[2]) | (switch[3] & ~switch[2] & ~switch[1]);

assign green = (switch[3] & ~switch[2] & switch[1]) | (switch[3] & switch[2]);

    

endmodule

---------------------

//right click simulation -> add verilog file

//testbench.v

`timescale 10ns / 1ps

module testbench;

//input

reg [3:0] switch = 0;

//output

wire red;

wire green;

wire blue;

//unit under test

rgb rgb(

    .switch(switch),

    .red(red),

    .green(green),

    .blue(blue)

);

integer k = 0;

initial

begin

    switch=0;

    

    for(k=0; k<16; k=k+1)

    #10 switch = k; //100ns

    

    #5 $finish;

end

endmodule

-----------------

//run behavioral simulation

step foward 0.1us, refresh button

drag and drop top left to zoom out, bottom right to zoom in

reference:

https://chuanshuoge3.blogspot.com/2022/04/vivado-2.html