crystal clock 100MZ
divided clock 5MZ
//clk_divider.v`timescale 1ns / 1ps
module clock_divider(
input wire clk,
output reg divided_clk=0
);
//division_value = clock frequency/(2*desired Frequency) - 1
//division_value = 100MHz/(2*5MHz) - 1 = 9
localparam div_value = 9;
//counter
integer counter_value = 0;
always@ (posedge clk)
begin
if(counter_value == div_value)
begin
counter_value <=0;
divided_clk <= ~divided_clk;
end
else
begin
counter_value <=counter_value+1;
divided_clk <= divided_clk;
end
end
endmodule
----------------------------
//testbench.v
`timescale 1ns / 1ps
module testbench;
reg clk = 0;
wire divided_clk;
clock_divider UUT(
.clk(clk),
.divided_clk(divided_clk)
);
always #5 clk = ~clk; //every 5ns signal flips => 10ns period => 100Mhz
endmodule
//top.v
`timescale 1ns / 1ps
module top(
input wire clk,
output wire led
);
endmodule
reference:
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