vivado shift register

//top.v

`timescale 1ns / 1ps

module top(

    input clk,

    input din,

    output reg [7:0] q

    );

    

always @ (posedge clk)

begin

    q[0] <=din;

    q[7:1]<=q[6:0];

end

endmodule

------------------------

//testbench.v

`timescale 1ns / 1ps

module testbench;

reg clk=0, din=0;

wire [7:0] q;

top UUT(clk, din, q);

initial begin

    #40 din = 1;

    #40 din = 0;

end

always #5 clk=~clk;

endmodule

reference:

https://www.youtube.com/watch?v=V9HPPUE3Yxs