vivado pwm

20%, 40%, 60%, 80% duty cycle

//top.v

`timescale 1ns / 1ps

module top(

    input clk,

    output [3:0] led

    );

    

//simple counter

reg[7:0] counter=0;

always@(posedge clk) begin

    if (counter<100) counter<=counter+1;

    else counter<=0;

end

//20% duty cycle

assign led[0] = (counter<20)?1:0;

//40% duty cycle

assign led[1] = (counter<40)?1:0;

//60% duty cycle

assign led[2] = (counter<60)?1:0;

//80% duty cycle

assign led[3] = (counter<80)?1:0;

endmodule

----------------------------

//testbench.v

`timescale 1ns / 1ps

module testbench;

reg clk=0;

wire led;

top UUT(clk, led);

always #5 clk=~clk;

endmodule

refernce:

https://www.youtube.com/watch?v=zNln9hJ5J78