main street A intersect local street B
Sa =1 when there are cars on main street
Sb = 1 when there are cars on local street
state = 0, main street light green, local street light red
state = 1, main street light yellow, local street light red
state = 2, main street light red, local street light green
state = 3, main street light red, local street light yellow
state = 0, when clock cycle is less than 6, or there is no traffic on local street
otherwise goes to state 1
stay in state 1 for 1 clock cycle, then go to state 2
state = 2 when clock cycle is less than 5, or there is no traffic on main street but lots of cars on local
otherwise goes to state 3
stay in state 3 for 1 clock cycle, then go to state 0
//trafficLight.v
`timescale 1ns / 1ps
module trafficLight(
input clk,
input sa,
input sb,
input reset,
output reg [2:0] la,
output reg [2:0] lb
);
reg [1:0] state; integer t=0;
always@(posedge clk, posedge reset)
begin
//light Green Yellow Red
if(reset) begin state<=2'b00; end
else begin
case (state)
2'b00: begin
la<=3'b100; lb<=3'b001;
t<=t+1;
if(t<6 | ~sb) state<=state;
else begin t<=0; state<=2'b01; end
end
2'b01: begin state<=2'b10; la<=3'b010; lb<=3'b001; end
2'b10: begin
la<=3'b001; lb<=3'b100;
t<=t+1;
if(t<5 | (~sa & sb)) state<=state;
else begin t<=0; state<=2'b11; end
end
2'b11: begin state<=2'b00; la<=3'b001; lb<=3'b010; end
endcase
end
end
endmodule
--------------------------
//testbench.v
`timescale 1ns / 1ps
module testbench;
reg clk=0, sa=0, sb=0, reset;
wire [2:0] la, lb;
trafficLight UUT(
.clk(clk),
.sa(sa),
.sb(sb),
.reset(reset),
.la(la),
.lb(lb));
always #5 clk=~clk;
initial begin
#10 reset=1;
#10 reset=0;
#80 sb = 1;
#100 sa = 1;
#250 sa = 0;
#50 sb = 0;
end
endmodule
reference:
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